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In semiconductor technology, copper interconnects are used in silicon integrated circuits (ICs) to reduce propagation delays and power consumption. Since copper is a better conductor than aluminium, ICs using copper for their interconnects can have interconnects with narrower dimensions, and use less energy to pass electricity through them. Together, these effects lead to ICs with better performance. They were first introduced by IBM, with assistance from Motorola, in 1997.
The transition from aluminium to copper required significant developments in fabrication techniques, including radically different methods for patterning the metal as well as the introduction of barrier metal layers to isolate the silicon from potentially damaging copper atoms.
Although some form of volatile copper compound has been known to exist since 1947, with more discovered as the century progressed, none were in industrial use, so copper could not be patterned by the previous techniques of photoresist masking and plasma etching that had been used with great success with aluminium. The inability to plasma etch copper called for a drastic rethinking of the metal patterning process and the result of this rethinking was a process referred to as an additive patterning, also known as a "Damascene" or "dual-Damascene" process by analogy to a traditional technique of metal inlaying.
In this process, the underlying silicon oxide insulating layer is patterned with open trenches where the conductor should be. A thick coating of copper that significantly overfills the trenches is deposited on the insulator, and chemical-mechanical planarization (CMP) is used to remove the copper (known as overburden) that extends above the top of the insulating layer. Copper sunken within the trenches of the insulating layer is not removed and becomes the patterned conductor. Damascene processes generally form and fill a single feature with copper per Damascene stage. Dual-Damascene processes generally form and fill two features with copper at once, e.g., a trench overlying a via may both be filled with a single copper deposition using dual-Damascene.
With successive layers of insulator and copper, a multilayer interconnect structure is created. The number of layers depends on the IC's function, 10 or more metal layers are possible. Without the ability of CMP to remove the copper coating in a planar and uniform fashion, and without the ability of the CMP process to stop repeatably at the copper-insulator interface, this technology would not be realizable.
A barrier metal layer must completely surround all copper interconnect, since diffusion of copper into surrounding materials would degrade their properties. For instance, silicon forms deep-level traps when doped with copper. As the name implies, a barrier metal must limit copper diffusivity sufficiently to chemically isolate the copper conductor from the silicon below, yet have high electrical conductivity in order to maintain a good electronic contact.
The thickness of the barrier film is also quite important; with too thin a layer, the copper contacts poison the very devices that they connect to; with too thick a layer, the stack of two barrier metal films and a copper conductor have a greater total resistance than aluminium interconnects, eliminating any benefit.
The improvement in conductivity in going from earlier aluminium to copper based conductors was modest, and not as good as to be expected by a simple comparison of bulk conductivities of aluminium and copper. The addition of barrier metals on all four sides of the copper conductor significantly reduces the cross-sectional area of the conductor that is composed of pure, low resistance, copper. Aluminium, while requiring a thin barrier metal to promote low ohmic resistance when making a contact directly to silicon or aluminium layers, did not require barrier metals on the sides of the metal lines to isolate aluminium from the surrounding silicon oxide insulators. Therefore scientists are looking for new ways to reduce the diffusion of Cu into Si substrates without using the buffer layer. One method is to use Cu-Ge alloy as the interconnect material so that buffer layer (e.g. TiN) is no longer needed. Epitaxial Cu3Ge layer has been fabricated with an average resistivity of 6 ± 1 μΩ cm and work function of ~4.47 ± 0.02 eV respectively, qualifying it as a good alternative to Cu.
Resistance to electromigration, the process by which a metal conductor changes shape under the influence of an electric current flowing through it and which eventually leads to the breaking of the conductor, is significantly better with copper than with aluminium. This improvement in electromigration resistance allows higher currents to flow through a given size copper conductor compared to aluminium. The combination of a modest increase in conductivity along with this improvement in electromigration resistance was to prove highly attractive. The overall benefits derived from these performance improvements were ultimately enough to drive full-scale investment in copper-based technologies and fabrication methods for high performance semiconductor devices, and copper-based processes continue to be the state of the art for the semiconductor industry today.
- "IBM100 - Copper Interconnects: The Evolution of Microprocessors". Retrieved 17 October 2012.
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- Wu, Fan; Cai, Wei; Gao, Jia; Loo, Yueh-Lin; Yao, Nan (2016-07-01). "Nanoscale electrical properties of epitaxial Cu3Ge film". Scientific Reports. 6: 28818. Bibcode:2016NatSR...628818W. doi:10.1038/srep28818. ISSN 2045-2322. PMC 4929471. PMID 27363582.
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