Low-κ dielectric

In semiconductor manufacturing, a low-κ is a material with a small relative dielectric constant relative to silicon dioxide. Although the proper symbol for the relative dielectric constant is the Greek letter κ (kappa), in conversation such materials are referred to as being "low-k" (low-kay) rather than "low-κ" (low-kappa). Low-κ dielectric material implementation is one of several strategies used to allow continued scaling of microelectronic devices, colloquially referred to as extending Moore's law. In digital circuits, insulating dielectrics separate the conducting parts (wire interconnects and transistors) from one another. As components have scaled and transistors have gotten closer together, the insulating dielectrics have thinned to the point where charge build up and crosstalk adversely affect the performance of the device. Replacing the silicon dioxide with a low-κ dielectric of the same thickness reduces parasitic capacitance, enabling faster switching speeds and lower heat dissipation.

Low-κ materials

The relative dielectric constant of SiO2, the insulating material still used in silicon chips, is 3.9. This number is the ratio of the permittivity of SiO2 divided by permittivity of vacuum, εSiO20,where ε0 = 8.854×10−6 pF/μm.[1] There are many materials with lower relative dielectric constants but few of them can be suitably integrated into a manufacturing process. Development efforts have focused primarily on the following classes of materials:

Fluorine-doped silicon dioxide

By doping SiO2 with fluorine to produce fluorinated silica glass, the relative dielectric constant is lowered from 3.9 to 3.5.[2] Fluorine-doped oxide materials were used for the 180 nm and 130 nm technology nodes.[3]

Organosilicate glass or OSG (Carbon-doped oxide or CDO)

By doping SiO2 with carbon, one can lower the relative dielectric constant to 3.0, the density to 1.4 g/cm3 and the thermal conductivity to 0.39 W/(m*K). The semiconductor industry has been using the organosilicate glass dielectrics since the 90 nm technology node.[4]

Porous silicon dioxide

Various methods may be employed to create voids or pores in a silicon dioxide dielectric.[3] Voids can have a relative dielectric constant of nearly 1, thus the dielectric constant of the porous material may be reduced by increasing the porosity of the film. Relative dielectric constants lower than 2.0 have been reported. Integration difficulties related to porous silicon dioxide implementation include low mechanical strength and difficult integration with etch and polish processes.

Porous organosilicate glass (carbon-doped oxide)

Porous organosilicate materials are usually obtained by a two-step procedure[4] where the first step consists of the co-deposition of a labile organic phase (known as porogen) together with an organosilicate phase resulting in an organic-inorganic hybrid material. In the second step, the organic phase is decomposed by UV curing or annealing at a temperature of up to 400°C, leaving behind pores in the organosilicate low-κ materials. Porous organosilicate glasses have been employed since the 45 nm technology node. [5]

Spin-on organic polymeric dielectrics

Polymeric dielectrics are generally deposited by a spin-on approach, which is traditionally used for the deposition of photoresist materials, rather than chemical vapor deposition. Integration difficulties include low mechanical strength, coefficient of thermal expansion (CTE) mismatch and thermal stability. Some examples of spin-on organic low-κ polymers are polyimide, polynorbornenes, benzocyclobutene, and PTFE.

Spin-on silicon based polymeric dielectric

There are two kinds of silicon based polymeric dielectric materials, hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ).

Air gaps

The ultimate low-k material is air with a relative permittivity value of ~1.0. However, the placement of air gaps between the conducting wires compromises the mechanical stability of the integrated circuit making it impractical to build an IC consisting entirely of air as the insulating material. Nevertheless, the strategic placement of air gaps can improve the chip's electrical performance without compromising critically its durability. For example, Intel uses air gaps for two interconnect levels in its 14 nm FinFET technology.[6]

See also

References

  1. ^ Sze, S. M. (2007). Physics of Semiconductor Devices. John Wiley & Sons. ISBN 978-0-471-14323-9.
  2. ^ Reynard, J (2002). "Integration of fluorine-doped silicon oxide in copper pilot line for 0.12-μm technology". Microelectronic Engineering. 60 (1–2): 113. doi:10.1016/S0167-9317(01)00586-X.
  3. ^ a b Hatton, Benjamin D.; Landskron, Kai; Hunks, William J.; Bennett, Mark R.; Shukaris, Donna; Perovic, Douglas D.; Ozin, Geoffrey A. (1 March 2006). "Materials chemistry for low-k materials". Materials Today. 9 (3): 22–31. doi:10.1016/S1369-7021(06)71387-6.
  4. ^ a b Shamiryan, D.; Abell, T.; Iacopi, F.; Maex, K. (2004). "Low-k dielectric materials". Materials Today. 7: 34–39. doi:10.1016/S1369-7021(04)00053-7.
  5. ^ Volksen, W.; Miller, R.D.; Dubois, G. (2010). "Low Dielectric Constant Materials". Chemical Reviews. 110 (1): 56–110. doi:10.1021/cr9002819. PMID 19961181.
  6. ^ James, Dick. "IEDM – Monday was FinFET Day". Chipworks.com. Retrieved 9 December 2018.

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